KEYNOTE #1
The challenges for high performance embedded
systems
Consumer electronics devices, such as digital TV sets, DVD
recorders, mobile phones, and other portable devices in the
areas of audio, video, and communication, traditionally rely on
application specific, non-programmable circuits for their
“streaming” part. This choice was dictated by constraints such
as limited power consumption budgets, silicon efficiency,
stringent real-time requirements, and low cost. Recent demands
on flexibility and reduced time-to-market of new products moved
the balance from dedicated circuits towards the use of
programmable components, dramatically increasing the software
content in products. However, the simultaneous increase in
performance requirements for stream-oriented processing excludes
the use of general-purpose processors, especially in the area of
advanced video processing (high end television sets for
example), and advanced radio communication (digital radio,
digital terrestrial TV, long-range wireless Internet access). As
a consequence, the combination of performance, flexibility,
power, and cost constraints creates a major gap between the
current programmable processors and the actual requirements of
applications. To bridge this gap, it is necessary to use
parallel architectures consisting of multiple, programmable
compute blocks, specifically designed for efficient processing
of data streams. However, accessing data is a major problem in
those systems, mainly because of the larger gap between access
time and compute time.
Programming highly parallel streaming architectures poses also
major challenges, both in term of correctness and in terms of
performance:
difficulty of achieving an efficient use of resources
(performance- and power-wise),
difficulty of managing different forms of parallelism,
difficulty and cost of debugging.
The
impact of the above challenges on development time and costs can
be reduced by the use of appropriate tools, which assist the
developer and automate many of his tasks to compensate the fact
that design complexity grow faster than designer productivity.
However, breakthroughs and improvements are required in:
-
Efficient exploitation of parallelism
available in applications,
-
Partitioning between hardware and software,
-
Efficient code generation for these new
architectures,
-
Reuse of source code for different target
systems.
Managing the ever-increasing complexity of embedded systems is
certainly one of the most important challenges beside power
consumption. Complexity will make systems unreliable and
unpredictable. We already reach the limits of validation by
simulation and worst-case design is no more affordable. Guided
by the principles of predictability and compositionality, we
will increasingly need to design reliable systems from uncertain
components, use higher abstraction level specification, formal
methods that allow “correct by construction” designs and
virtualization of (shared) resources allowing a "separation of
concerns".
The
new technology nodes (65nm, soon 45nm) will also bring their own
challenges: the global interconnect delay does not scale with
logic, and the scaling for clock speed is no more valid. Also
the increasing variability of components (leading to design –
such as timing closure - and yield problems) perhaps requires
self-correcting systems, allowing and compensating for errors.
The leakage power will also pose a major problem for the design
of complex systems, leading to innovative solutions like power
gating at much finer grain than core level.
All
these challenges show the need of a multidisciplinary approach
to the development of high quality embedded systems and
therefore the importance of sharing knowledge in architectures,
methods and tools like it is addressed in the Euromicro
Conference on Digital System Design.
Dr. Marc Duranton
Principal Scientist
Embedded Systems Architectures on Silicon (ESAS)
Philips Research - Room 3.33
High Tech Campus 31 - 5656 AE Eindhoven
The
Netherlands
Phone: +31 40 27 45426 - Fax: +31 40 27 44639
Email: marc.duranton@philips.com
Biography:
Dr.
Marc Duranton is a principal scientist in the Embedded Systems
Architectures on Silicon Group of Philips Research. He has two
MSc degrees in electrical engineering, and computer science from
Ecole Nationale Supérieure d'Electronique et de Radioélectricité
de Grenoble, and Ecole Nationale Supérieure d'Informatique et de
Mathématiques Appliquées de Grenoble, respectively, and a PhD
(1995) from Institut National Polytechnique de Grenoble, all in
France. He worked within Philips Semiconductors in California on
several video coprocessors for the TriMedia and Nexperia
platforms and is currently working on the next generation
compute engine for Philips platform. His research interests
include parallel and high performance architectures for video
and image processing, system modeling and validation, software
optimization and compiler technology. He has published several
articles and book chapters, and more than 20 patents. He has
supervised 4 PhD students and more than 10 MSc students, and has
given courses in several engineering schools in France.
KEYNOTE #2
“Digital RF”
Roman Staszewski, Texas Instruments
Something very special happened at the turn of the last century.
It didn’t get nearly as much news coverage as the millennium
bug, but its impact will be experienced by most people on earth.
In fact, it was a low key phenomenon that received attention
only from few technologists. This phenomenon was the ability to
reliably scale a CMOS transistor below a certain size, so it
could digitally switch at RF frequency rate. This is when
“Digital RF” was born. This opened new doors to how wireless
communication could be implemented – reliably and inexpensively.
The RF circuits finally entered the physics of Moore’s Law. This
is nothing short of a paradigm change of RF radio design,
benefits of which will be enjoyed by billions of people
worldwide instead of privileged millions.
In
this presentation, I will describe in the rationale behind this
new paradigm. I will overview how Texas Instruments has
manifested Digital RF in its Digital Radio Processor (DRP)
technology.
Both digital and RF/analog designers can claim they have proven
and sufficient design methodologies. The luxury of isolation let
them perfect their own world without any concern for the other.
But, the world demands efficiency, the latest technology for
pennies. While tight integration of RF and digital in SOC is the
cost effective answer, it opens a design methodology Pandora
Box. What previously could be ignored, has to be considered.
What was proven and sufficient, may not work anymore. The
resulting paradigm change affects all aspects of the design
process from system architecture to circuit design to validation
to test. I will describe some of the challenges that have been
solved and those remaining to be researched.
Roman Staszewski
Design Manager
Senior Member Technical Staff
DRP
Design, WTBU
roman-s@ti.com
(214)567-7133
Roman Staszewski received his B.S.E.E degree with summa cum
laude honors from the University of Texas at Dallas in 1992. He
earned M.S.E.E. degree from the same university in 1995.
In
1993, he joined Texas Instruments in Dallas where he had been
engaged in design of various mixed signal, ultra-high-speed
digital and VLSI products, such as color monitor DAC drivers,
video encoders and decoders, 3D graphics controllers, and
security RFID SOC’s.
In
2000, he joined the Digital Radio Processor (DRP) startup team
as one of few principal members to define digital architecture,
validation, and physical implementation methodologies of fully
integrated RF radio SOC’s in advanced deep-submicron CMOS
technologies. This work resulted in mass production of
single-chip solutions of Bluetooth and GSM phone products.
His
current research focuses on product-driven extension of the DRP
digital architecture to more advanced cellular and other
communication standards. It also involves inventing
architectures that allow software reconfigurable multi-mode and
multi-standard RF radios, taking advantage of the future
deep-submicron CMOS process capabilities.
He
is currently a Senior Member of Technical Staff at Texas
Instruments, based in Dallas, Texas.
KEYNOTE #3
“Deep sub-100 nm Design Challenges”
Moore’s law and the scaling theory have been the guiding
principles for the semiconductor industry to accomplish its
rapid progress and persistent growth. Semiconductor chips had
been continuously benefited from the device scaling by
simultaneously achieving higher density, higher performance and
lower power consumption until they reached the 100 nm technology
node. However, once the silicon technology exceeded this point,
i.e. in sub-100 nm nodes, some important device parameters have
started to deviate from the scaling theory, such as threshold
voltages and leakage currents. As a result, we are able to enjoy
only higher density from the device scaling, but neither higher
performance nor lower power any longer especially at the deep
sub-100 nm nodes.
In addition, the increase in device density has created
various new problems. A single LSI chip can accommodate more
number of gates than the engineers can properly design and
integrate in a reasonable time period. This gap causes a serious
design efficiency problem. Another problem is the large power
consumption of the chip both in operation and stand-by. Even
though the LSI design and initial development are successful,
highly integrated chips will face yield problems in the volume
production. Yield learning and quick yield ramp are crucial
especially when the product life time is short, which is usually
the case for digital media SoC’s (System on Chip).
This presentation will describe the problems mentioned above and
will discuss several approaches to counteract these problems,
such as high-level language and platform based design flow,
various low power technologies from device, circuit to
architecture view points, and DFM (Design for Manufacturing)
related technologies.
Tohru Furuyama
General Manager
Center for Semiconductor Research and Development
Semiconductor Company
Toshiba Corporation
Phone: +81-44-548-2522
Fax: +81-44-548-8324
email: tohru.furuyama@toshiba.co.jp
Tohru Furuyama received the B.S. and Ph.D.
degrees from the University of Tokyo, Tokyo, Japan, the M.S.
degree from Cornell University, Ithaca, NY, USA.
Dr. Furuyama led several commodity DRAM and
Rambus DRAM developments and a embedded DRAM project for
graphics applications at the Semiconductor Device Engineering
Laboratory (SDEL), Toshiba Corp. He also conducted researches on
new circuit techniques including sense amplifiers and studies on
reliability issues, such as α-particle induced soft errors, hot
carrier related problems and wafer level burn-in technologies.
From 1994 to 1996, he was the 64Mb DRAM design manager for the
Toshiba/IBM/Siemens trilateral joint DRAM development project at
Burlington, VT. He was then a senior manager at the System LSI
Engineering Laboratory, Toshiba Corp, where he was responsible
for the developments of Toshiba’s original “Media embedded
Processor” (MeP), MPEG-4 codec LSI’s for mobile applications
that utilized the eDRAM technology he had established as a
project leader, and so on. In 2002, he was appointed to a
general manager of the SoC Research & Development Center (SoCC),
Toshiba Corp., where he supervised various R&D activities;
advanced CMOS technologies, NAND flash memories, embedded
memories, novel memories, embedded processors (MeP), digital
media SoC’s and related softwares. He is presently a general
manager of the Center for Semiconductor Research & Development (CSRD),
which was re-organized from SoCC in April, 2006.
Dr. Furuyama is an IEEE Fellow.
KEYNOTE #4
New Directions in Mobile Device Architectures
Mobile device industry is going to face a significant disruption
in coming years due to maturing era of digital convergence. The
whole mobile industry need to go through profound transformation
from vertical to horizontal business model. This transformation
will have deep impacts on architectures, platforms and design
approach.
Mobile device industry is currently facing a trend in which the
borders between information technology industries are gradually
vanishing. Five years ago digital camera was digital camera, PC
was computer, mobile phone was a phone. Today we still have
those product categories but at the same time you can find more
and more new products that are difficult to categorize. PDAs are
to some extend portable computers but enhanced communication
features will bring them quite close to phones. Smart phone with
high end multimedia processing capabilities turns out to be
advanced MP3 player. And these are only the first steps in this
road. This kind of diversification is introducing new set of
requirements for architectures and platforms. Obvious ones are
flexibility, scalability, and modularity
One
consequence of current development is the increased
horizontalization in digital convergence industry. Requirement
to master more divergent technologies is leading towards
specialization and along with modularity this will lead to
emergence of horizontal technology markets. Of course, to make
this happen we need to also adopt open interfaces either through
standardization or through de facto industry standards with open
specification - not forgetting the open source community with
increasing exposure towards mobile platforms.
Modularity enables horizontal technology market and horizontal
module business gradually implies the birth of dominant
platform(s). This has been seen happening in PC industry in
early eighties. It is true that many things are different in
mobile devices compared to PCs but nevertheless the dynamics of
the business will push the development towards one dominant
mobile device architecture and corresponding platforms. Triplet
- modularity-horizontal technology market-dominant platform are
very much interlinked and it would be very challenging to try to
create artificially such a phenomenon but when it starts to
emerge it will also be very hard to stop. Currently many
inherent drivers in mobile device industry are pushing towards
modular solutions, standardized interfaces, and utilization of
third parties with special domain knowledge
In
this keynote talk I am going to go through the key requirements
for future mobile platforms and also share some of our thinking
of coming new mobile architectures.
Dr.
Risto Suoranta
Research Fellow, Nokia
Dr.
Suoranta was born in Hämeenlinna, Finland, in 1958. He received
his M.Sc degree in electrical engineering from Tampere
University of Technology (TUT) in 1984; degree of Lic. Tech in
1990 from TUT and his Dr. Tech degree in 1995 also from TUT.
Dr. Suoranta has been widely involved in both applied and
theoretical research in the area of digital signal processing.
He has involved in the research of medical signal processing,
sensor signal processing in the field of mobile robotics and
applied research of system engineering in the area of
telecommunication systems.
From 1984 to 1995 he was employed by VTT with the positions of
research scientist, leader o f the research group and the head
of the research area. Since 1995 Dr. Suoranta has been working
in Nokia Research Center in positions of Research Manager,
principal scientist, research fellow and deputy head of
Electronics Laboratory
His expertise covers several areas of digital signal processing
including signal and spectrum analysis, signal and system
modeling and implementations of DSP based systems. He has been
strongly involved in the research of a nonlinear digital
filtering, amplitude domain filtering and image processing. In
Nokia Dr. Suoranta has lead several technology programs to
develop 3G baseband solutions including system engineering and
implementation. Currently he is heading mobile device
architecture renewal research activities in Nokia research.
