|
|
SESSION 1 |
SESSION 2 |
SESSION 3 |
|
|
KEYNOTES |
INVITED |
LONG PRESENTATION |
|
|
SHORT PRESENTATION |
POSTER PRESENTATIONS |
|
|
|
|
|
|
|
|
T1 |
Systems-on-a-chip/in-a-package |
|
|
T2 |
Programmable/re-configurable
architectures |
|
|
T3 |
System, hardware and embedded software
specification, modeling and validation |
|
|
T4 |
System, hardware and embedded software
synthesis |
|
|
T5 |
Emerging technologies, system paradigms
and design methodologies |
|
|
T6 |
Applications of Digital systems |
|
|
RAWSN SS |
Resource-Aware Sensor Network Systems |
|
|
LPHPNOC SS |
Low-Power and High-Performance
Networks-on-Chip
|
|
|
|
|
|
|
|
|
|
|
|
DAY I |
WED |
|
|
|
|
|
|
8:30 AM - 9:30 AM |
REGISTRATION |
|
9:30 AM - 10:00 AM |
OPENING |
|
|
|
|
|
|
10:00 AM - 11:00 AM |
KEYNOTE I - The challenges for high
performance embedded system - Marc Duranton (DSD) |
|
|
|
|
|
|
11:00 AM -11:30 AM |
COFFEE BREAK |
|
|
|
|
|
|
11:30 AM - 12:30 PM |
KEYNOTE II - Moving Architectural
Description from Under the Technology Lamppost - Nenad
Medvidović (SEAA) |
|
|
|
|
|
|
|
|
|
|
|
12:30 PM - 2:00 PM |
LUNCH |
|
|
|
|
|
|
|
|
|
|
|
2:00 PM - 3:00 PM |
KEYNOTE III - Deep sub-100 nm Design
Challenges - Tohru Furuyama (DSD) |
|
|
|
|
|
|
3:00 PM - 4:45 PM |
SESSION 1 |
|
|
T41 |
RAWSN SS 1 |
LPHPNOC SS 1 |
|
|
Quality-driven Template-based
Architecture Synthesis for Real-time Embedded SoCs --
Lech Jozwiak*, Sien-An Ong |
Improving Delivery Ratio and Power
Efficiency in Unicast Geographic Routing with a
Realistic Physical Layer for Wireless Sensor Networks --
Juan A. Sanchez, Pedro M. Ruiz |
A simple clockless Network-on-Chip for a
commercial audio DSP chip. -- Tobias Bjerregaard,
Johnny Halkjaer Pedersen, Jens Sparsoe*, Mikkel Bystrup
Stensgaard* |
|
|
A Unified Architecture for H.264 Multiple
Block-Size DCT with Fast and Low Cost Quantization --
Javier D. Bruguera, Roberto R. Osorio* |
Opportunistic Pervasive Computing with
Domain-oriented Virtual Machines
-- J. Domaszewicz*, M.
Rój, A. Pruszkowski |
Adaptive Power Management for the On-Chip
Communication Network -- Liang Guang*, Axel Jantsch* |
|
|
Rachael SPARC: An Open Source 32-bit
Microprocessor Core for SoCs -- Michael Cowell*, Adam
Postula* |
Lifetime Analysis in Heterogeneous Sensor
Networks -- Falko Dressler*,
Isabel Dietrich |
Packetizing OCP Transactions in the MANGO
Network-on-Chip -- Tobias Bjerregaard, Jens Sparsa* |
|
|
Comparing the Performance of a 64-bit
Fully-Asynchronous Superscalar Processor versus its
Synchronous Counterpart -- Jose Manuel Colmenar, Oscar
Garnica, Jose Ignacio Hidalgo, Juan Lanchares*,
Guadalupe Miana |
ALDEC PRESENTATION
4:30 - 5:00 PM |
Designing Efficient Irregular Networks
for Heterogeneous Systems-on-Chip -- Christian Neeb*,
Norbert Wehn |
|
|
|
|
A High Level Power Model for the Nostrum
NoC -- Axel Jantsch*, Sandro Penolazzi |
|
|
|
|
Off-line Testing of Delay Faults in NoC
Interconnects -- Tomas Bengtsson*, Artur Jutman,
Shashi Kumar*, Zebo Peng, Raimund Ubar |
|
|
|
|
|
|
4:45 PM - 5:15 PM |
COFFEE BREAK |
|
|
|
|
|
|
|
|
|
|
|
5:15 PM - 6:15 PM |
SESSION 2 |
|
|
T40 |
T51 |
LPHPNOC SS 2 |
|
|
Flexible Two-Level Boolean Minimizer
BOOM-II and Its Applications -- Petr Fiser*, Hana
Kubatova* |
Performance Improvement for H.264 Video
Encoding using ILP Embedded Processor -- Ali Iranpour*,
krzysztof kuchcinski |
Flexible Bus and NoC Performance Analysis
with Configurable Synthetic Workloads -- Axel Jantsch*,
Ingo Sander, Rikard Thid* |
|
|
DSOP: Synthesis of a new class of regular
functions -- Anna Bernasconi*, Valentina Ciriani |
Function Call Optimization in Behavioral
Synthesis -- Yuko Hara*, Shinya Honda, Hiroaki
Takada, Hiroyuki Tomiyama* |
Energy Reduction through Crosstalk
Avoidance Coding in NoC Paradigm -- Amlan Ganguly,
Cristian Grecu, Partha Pratim Pande*, Haibo Zhu |
|
|
Multi-objective Optimal FSM State
Assignment -- Lech Józwiak, Aleksander Slusarczyk,
Dominik Gawlowski* |
DESIGN GUIDES FOR A CORRECT DC OPERATION
IN RTD-BASED THRESHOLD GATES -- Maria J. Avedillo,
Hector Pettenghi, Jose M. Quintana* |
Deadlock Free Routing Algorithms for Mesh
Topology NoC Systems with Regions -- Rickard Holsmark*,
Shashi Kumar*, Maurizio Palesi |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
7:00 PM |
COCKTAIL/RECEPTION |
|
|
|
|
|
|
|
|
|
|
|
DAY2 |
THUS |
|
|
|
|
|
|
|
|
|
|
|
8:30 AM - 10:00 AM |
SESSION 3 |
|
|
T12 |
RAWSN SS 2 |
T21 |
|
|
Towards Performance-oriented
Pattern-based Refinement of Synchronous Models onto NoC
Communication -- Zhonghai Lu, Ingu Sander, Axel Jantsch |
Wireless Medical Information System
Network for Patient ECG Monitoring -- Matthew DSouza,
Adam Postula*, Montserrat Ros |
Dependable Design for FPGA based on
Duplex System and Reconfiguration -- Radek Dobias,
Pavel Kubalik, Hana Kubatova* |
|
|
Resource-efficient Routing and Scheduling
of Time-constrained Network-on-Chip Communication --
Twan Basten, Marc Geilen, AmirHossein Ghamarian,
Sander Stuijk*, Bart Theelen |
Voltage Sensors for Supply Capacitor in
Passive UHF RFID Transponders -- R Berenguer, A
Garcia-Alonso, J A Montiel-Nelson*, R Morales* |
A Multi-Standard Reconfigurable Viterbi
Decoder using Embedded FPGA blocks -- Giuseppe Baruffa,
Lucia Bissi*, Pisana Placidi, Andrea Scorzoni |
|
|
On cache coherency and memory consistency
issues in NoC based shared memory multiprocessor SoC
architectures -- Frédéric Pétrot, Alain Greiner, Pascal
Gomez |
Improved Precision of Coarse Grained
Localization in Wireless Sensor Networks -- Jan
Blumenthal, Frank Reichenbach*, Dirk Timmermann |
|
|
|
PARTITION BASED DYNAMIC 2D HW
MULTITASKING MANAGEMENT -- Hortensia Mecha, Daniel
Mozos, Sara Roman*, Julio Septien |
|
|
|
|
|
|
|
|
|
|
|
|
|
10:00 AM - 10:30 AM |
COFFEE BREAK |
|
|
|
|
|
|
10:30 AM - 11:30 AM |
|
